Title :
A delay model and optimization method of a low-power BiCMOS logic circuit
Author :
Zhang, Shayan ; Kalkur, T.S. ; Lee, Steven ; Gatza, Lori
Author_Institution :
Dept. of Electr. & Comput. Eng., Colorado Univ., Colorado Springs, CO, USA
fDate :
10/1/1994 12:00:00 AM
Abstract :
A new delay model and optimization method is proposed for a low-power BiCMOS driver. A transient overdrive, base directly-tied complementary BiCMOS logic circuit operates faster than conventional BiCMOS and CMOS circuits for supply voltage down to 1.5 V by using a speed-power-area optimization approach. An analytical delay expression is derived for the first time for a full-swing BiCMOS circuit with short-channel effects. The circuit is simulated with a HSPICE model using 0.8-μm BiCMOS technology with a 6-GHz n-p-n and a 1-GHz p-n-p transistor. The simulation results have verified the analytical results and demonstrated that the circuit can work up to 200 MHz operating frequency for a load capacitance of 1 pF at 1.5 V of supply voltage
Keywords :
BiCMOS integrated circuits; SPICE; circuit CAD; circuit analysis computing; delays; equivalent circuits; integrated logic circuits; logic CAD; logic design; optimisation; 0.8 micron; 1 pF; 1.5 V; 200 MHz; BiCMOS driver; CAD; HSPICE model; base directly-tied complementary; delay model; full-swing BiCMOS circuit; low-power BiCMOS logic circuit; optimization method; short-channel effects; simulation; speed-power-area optimization approach; transient overdrive; BiCMOS integrated circuits; CMOS logic circuits; CMOS technology; Circuit simulation; Delay effects; Driver circuits; Logic circuits; Optimization methods; Semiconductor device modeling; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
