Optimization-based placement algorithm for BiCMOS leaf cell generation

We present a transistor placement algorithm for the automatic layout synthesis of logic and interface cells comprised of a mixture of MOS and bipolar devices. Our algorithm is applicable to BiCMOS logic cells, ECL logic cells as well as TTL, CMOS and ECL compatible input/output (I/O) cells. The transistor placement problem is transformed into a layout floorplan design problem with a mixture of rigid and flexible modules. A constructive “branch-and-bound” algorithm is used to minimize the area of synthesized circuits subject to pre-placement constraints. Experimental results indicate that the algorithm can produce efficient placements under fixed-height constraints. The design space exploration mechanism can be controlled by the user so as to apportion computing resources judiciously