Title :
Corner bonding of CSPs: processing and reliability
Author :
Tian, Guoyun ; Liu, Yueli ; Johnson, R. Wayne ; Lall, Pradeep ; Palmer, Mike ; Islam, Mohd Nokibul ; Crane, Lawrence
Author_Institution :
Electr. & Comput. Eng. Dept., Auburn Univ., AL, USA
fDate :
7/1/2005 12:00:00 AM
Abstract :
The use of chip-scale packages (CSPs) has expanded rapidly, particularly in portable electronic products. Many CSP designs will meet the thermal cycle or thermal shock requirements for these applications. However, mechanical shock (drop) and bending requirements often necessitate the use of underfills to increase the mechanical strength of the CSP-to-board connection. Capillary flow underfills processed after reflow provide the most common solution to improving mechanical reliability. However, capillary underfill dispense, flow, and cure steps and the associated equipment add cost and complexity to the assembly process. Corner bonding provides an alternate approach. Dots of underfill are dispensed at the four corners of the CSP site after solder paste print but before CSP placement. During reflow, the underfill cures, providing mechanical coupling between the CSP and the board at the corners of the CSP. Since only small areas of underfill are used, board dehydration is not required. This paper examines the manufacturing process for corner bonding including dispense volume, CSP placement, and reflow. Drop test results are then presented. A conventional, capillary process was used for comparison of drop test results. Test results with corner bonding were intermediate between complete capillary underfill and nonunderfilled CSPs. Finite-element modeling results for the drop test are also included.
Keywords :
chip scale packaging; finite element analysis; impact testing; integrated circuit bonding; integrated circuit manufacture; integrated circuit testing; reflow soldering; CSP design; CSP placement; CSP-to-board connection; assembly process; bending requirements; board dehydration; capillary flow underfills; capillary process; chip-scale packages; corner bonding; dispense volume; drop test; finite element modeling; manufacturing process; mechanical coupling; mechanical reliability; mechanical shock; mechanical strength; portable electronic products; reflow; solder paste; thermal cycle; thermal shock requirement; Assembly; Bonding; Chip scale packaging; Costs; Electric shock; Electronic packaging thermal management; Manufacturing processes; Product design; Rapid thermal processing; Testing; Chip-scale packaging; chip-scale package (CSP); drop testing; underfill;
Journal_Title :
Electronics Packaging Manufacturing, IEEE Transactions on
DOI :
10.1109/TEPM.2005.852234