Title :
Low supply voltage operation of over-40-Gb/s digital ICs based on parallel-current-switching latch circuitry
Author :
Amamiya, Yasushi ; Yamazaki, Zin ; Suzuki, Yasuyuki ; Mamada, Masayuki ; Hida, Hikaru
Author_Institution :
Syst. Devices Res. Labs., NEC Corp., Ibaraki, Japan
Abstract :
We implemented a low-voltage latch circuit topology in a full-rate 4:1 multiplexer (MUX) using InP-HBT technology. The proposed latch circuitry incorporates parallel current switching together with inductive peaking a combination that makes it suitable for over-40-Gb/s operation at supply voltages ranging from 1.5 to 1.8 V. The full-rate 4:1 MUX provided 40-Gb/s error-free operation with a power dissipation of only 1 W at a supply voltage of 1.8 V. The D-flip/flop (D-F/F) based on this latch circuitry provided 50-Gb/s D-F/F operation at a supply voltage as low as 1.5 V. Demultiplexing operation was also confirmed for the D-F/F with this circuit technology at a data rate of up to 110Gb/s with a 1.8-V supply voltage. The latch circuitry should help enable development of a low-voltage 40-Gb/s full-rate module which can be seamlessly connected with high-speed CMOS I/O circuits.
Keywords :
III-V semiconductors; demultiplexing; digital integrated circuits; flip-flops; heterojunction bipolar transistors; high-speed integrated circuits; indium compounds; low-power electronics; multiplexing equipment; network topology; 1 W; 1.5 to 1.8 V; 50 Gbit/s; CMOS I/O circuits; D-F/F; D-flip/flop; InP; InP-HBT technology; MUX; demultiplexing; digital IC; full-rate module; high-speed circuits; inductive peaking; latch circuit topology; low power dissipation; low supply voltage; multiplexer; parallel current switching; CMOS technology; Circuit topology; Clocks; Demultiplexing; Digital circuits; Latches; Low voltage; Multiplexing; Personal communication networks; Power dissipation; High speed; InP HBT; low power dissipation; low supply voltage; multiplexer;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2005.854593
