Limitations of switch level analysis for bridging faults

Author

Rajsuman, Rochit ; Malaiya, Yashwant K. ; Jayasumana, Anura P.

Author_Institution

Dept. of Comput. Eng., Case Western Reserve Univ., Cleveland, OH, USA

Volume

8

Issue

7

fYear

1989

fDate

7/1/1989 12:00:00 AM

Firstpage

807

Lastpage

811

Abstract

Switch-level models are widely used for fault analysis of MOS digital circuits. Switch-level analysis (SLA) provides significantly more accurate results compared to gate-level models, and also avoids the complexities of circuit-level analysis. The accuracy of SLA is critically examined, and conditions under which SLA may generate incorrect results are specified. Such conditions may occur when the bulk of a transistor is connected to its source. These conditions are especially applicable under certain types of bridging faults. A simple technique is suggested for accurate switch-level modeling under such conditions

Keywords

CMOS integrated circuits; MOS integrated circuits; digital integrated circuits; integrated circuit testing; logic testing; CMOS gate; MOS digital circuits; NMOS gate; accurate switch-level modeling; bridging faults; fault analysis; switch level analysis; Circuit analysis; Circuit faults; Circuit simulation; Digital circuits; Electric resistance; MOS devices; Switches; Switching circuits; Testing; Voltage;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.31538

Filename

31538