Improved gate matrix layout

A two-stage approach to gate matrix layout is described. The approach consists of: the determination of an optimal gate sequence and an assignment of nets to rows such that the nets are realizable. The gate sequence algorithm is based on T. Asano´s approximate search (1981). Modifications are made to it to take into account constraints of transistor sizing, serial subcircuit conflicts, input/output (I/O) gates, and I/O nets. The zone-net assignment algorithm assigns nets to a minimum number of rows determined by the gate sequence and provides a means to resolve vertical conflicts in the layout. Power connections are implemented using the power nets and possible added power rows. Results of examples show that the approach can achieve a considerable improvement compared to earlier algorithms, while satisfying additional constraints