Title :
Small-signal analysis and minimum settling time design of a one-stage folded-cascode CMOS operational amplifier
Author :
Yang, Howard C. ; Abu-Dayeh, Mahmoud A. ; Allstot, David J.
Author_Institution :
Chips & Technol., Inc., San Jose, CA, USA
fDate :
7/1/1991 12:00:00 AM
Abstract :
A small-signal analysis of the single-ended one-stage folded-cascode CMOS operational amplifier is presented. The analysis results in a four-pole two-zero representation from which a two-pole model is extracted that is sufficiently accurate for many applications in switched-capacitor (SC) circuits. A design equation for obtaining the minimum settling time (MST) response for SC applications is given
Keywords :
CMOS integrated circuits; linear integrated circuits; operational amplifiers; SC applications; four-pole two-zero representation; minimum settling time design; one-stage folded-cascode CMOS operational amplifier; small-signal analysis; switched capacitor circuits; two-pole model; Circuits; Entropy; Equations; Frequency; Operational amplifiers; Semiconductor device modeling; Sensor arrays; Signal processing algorithms; Spectral analysis; Speech processing;
Journal_Title :
Circuits and Systems, IEEE Transactions on
