Title :
Two-dimensional analysis of a merged BiPMOS device
Author :
Kuo, J.B. ; Rosseel, G.P. ; Dutton, R.W.
Author_Institution :
Center of Integrated Syst., Stanford Univ., CA, USA
fDate :
8/1/1989 12:00:00 AM
Abstract :
The BiPMOS device associated with n-well BiCMOS technologies consumes a substantial area for isolation. A merged BiPMOS device structure is introduced to reduce the device size for BiCMOS VLSI. The performance of the merged BiPMOS device has been analyzed using PISCES-2B, a program for solving Poisson and continuity equations. Comparisons between the merged BiPMOS device and a conventional one show that the merged BiPMOS device, which occupies a much smaller area, has a comparable performance
Keywords :
BIMOS integrated circuits; VLSI; circuit analysis computing; BiCMOS; BiPMOS; PISCES-2B; Poisson equations; VLSI; circuit analysis computing; continuity equations; BiCMOS integrated circuits; Councils; Degradation; Design automation; Electrodes; Helium; Inverters; MOS devices; Very large scale integration; Voltage;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
