Title :
Minimizing pattern count for interconnect test under a ground bounce constraint
Author :
Marinissen, Erik Jan ; Vermeulen, Bart ; Hollmann, Henk ; Bennetts, R.G.
Author_Institution :
Philips Res. Labs., Eindhoven, Netherlands
Abstract :
When testing the interconnect structures on a board, test programmers sometimes ask, How can I control the test pattern generation process to avoid ground bounce problems during Extest mode? Those wishing to satisfy a simultaneously-switching-outputs constraint will find several new solutions in this article.
Keywords :
automatic test pattern generation; circuit testing; integrated circuit interconnections; integrated circuit testing; interconnect structures; interconnect test; interconnect test generation; test engineers; test generation; test patterns; Communication system control; Fault detection; Hamming distance; Laboratories; Mobile communication; Power generation; Programming profession; Test pattern generators; Testing;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.2003.1188257
