Title :
A design-for-verification technique for functional pattern reduction
Author :
Liu, Chien-Nan Jimmy ; Chen, I-Ling ; Jou, Jing-Yang
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
This technique reduces the number of required functional patterns by first defining conditions for hard-to-control (HTC) code in a hardware-description-language design and then using an algorithm to detect such code automatically. A second algorithm eliminates these HTC points by selecting a minimum number of nodes for control point insertion.
Keywords :
circuit layout CAD; formal verification; hardware description languages; design-for-verification technique; functional pattern reduction; hard-to-control code; hardware-description-language design; Automatic testing; Circuit faults; Circuit simulation; Circuit testing; Design engineering; Design for testability; Hardware design languages; Manufacturing processes; Test pattern generators; Virtual manufacturing;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.2003.1188262
