A 200-MHz 16-bit super high-speed signal processor (SSSP) LSI

Author

Yamashina, Masakazu ; Goto, Junichi ; Okamoto, Fuyuki ; Ando, Kouichi ; Yamada, Hachiro ; Horiuchi, Tadahiko ; Nakamura, Kimiko ; Enomoto, Tadayoshi

Author_Institution

NEC Corp., Kanagawa, Japan

Volume

24

Issue

6

fYear

1989

fDate

12/1/1989 12:00:00 AM

Firstpage

1668

Lastpage

1674

Abstract

A 200-MHz 16-b BiCMOS super high-speed signal processing (SSSP) circuit has been developed for high-speed digital signal processor (DSP) LSIs. In order to produce extremely fast LSI circuits, several novel techniques have been combined for integration of the SSSP. They include a redundant binary convolver architecture, a double-stage pipelined convolver architecture, and submicrometer BiCMOS drivers with large capacitive load drivability. The SSSP performs 200-MHz addition. The chip, which was fabricated with 0.8-μm BiCMOS and triple-layer metallization technology, has an area of 5.87 mm×5.74 mm and contains 20150 transistors. It operates at a clock frequency of 200 MHz with a single 5-V power supply and typically consumes 800 mW

Keywords

BIMOS integrated circuits; digital signal processing chips; large scale integration; pipeline processing; redundancy; 0.8 micron; 16 bit; 200 MHz; 5 V; 800 mW; BiCMOS; DSP; LSI; capacitive load drivability; clock frequency; digital signal processor; double-stage pipelined convolver architecture; redundant binary convolver architecture; single 5-V power supply; submicron drivers; super high-speed; triple-layer metallization; BiCMOS integrated circuits; Clocks; Convolvers; Digital signal processing; Digital signal processing chips; Digital signal processors; Driver circuits; Large scale integration; Metallization; Signal processing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.45004

Filename

45004