• DocumentCode
    1163863
  • Title

    Deep-level dominated current-voltage characteristics of buried implanted oxide silicon-on-insulator

  • Author

    Das, K. ; Palmour, J.W. ; Posthill, J.B. ; Humphreys, T.P. ; O´Sullivan-French, J. ; Byrd, N.Y. ; Lu, D. ; Wortman, J.J. ; Parikh, N.R.

  • Author_Institution
    Dept. of Mater. Sci., North Carolina State Univ., Raleigh, NC, USA
  • Volume
    10
  • Issue
    3
  • fYear
    1989
  • fDate
    3/1/1989 12:00:00 AM
  • Firstpage
    135
  • Lastpage
    137
  • Abstract
    Current-voltage characteristics of Au contacts formed on buried implanted oxide silicon-on-insulator (SOI) structures are discussed, which indicate that the dominant transport mechanism is space-charge-limited current (SCLC) conduction in the presence of deep-level states. The deep-level parameters, determined using a simple analysis, appear to be sensitive to anneal conditions used and subsequent processing. Silicon implanted with 1.7*10/sup 18/ cm/sup -2/ oxygen ions at 150 keV following a 1200 degrees C anneal for 3 h shows deep level 0.37 eV below the conduction band edge with a concentration of unoccupied traps of approximately 2*10/sup 15/ cm/sup -3/. In contrast, arsenic ion implantation, in the 1200 degrees C annealed material with a dose of 1.5*10/sup 12/ cm/sup -2/ at 60 keV and activated by rapid thermal annealing (RTA), introduces a deep level 0.25 eV below the conduction band edge with an unoccupied trap concentration of approximately 6*10/sup 17/ cm/sup -2/.<>
  • Keywords
    annealing; arsenic; deep levels; elemental semiconductors; gold; oxygen; silicon; space-charge-limited conduction; 1200 degC; 150 keV; 60 keV; Au-Si:As; Au-Si:O; anneal conditions; buried implanted oxide silicon-on-insulator; conduction band edge; current-voltage characteristics; deep-level states; rapid thermal annealing; space-charge-limited current; transport mechanism; unoccupied trap concentration; Conducting materials; Current-voltage characteristics; Dielectric materials; Gold; Ion implantation; Materials science and technology; Rapid thermal annealing; Silicon on insulator technology; Substrates; Temperature;
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/55.31693
  • Filename
    31693