Boron channel-stop design for poly-buffered LOCOS using selective boron segregation

Author

Pfiester, James R.

Author_Institution

Motorola Inc., Austin, TX, USA

Volume

10

Issue

4

fYear

1989

fDate

4/1/1989 12:00:00 AM

Firstpage

147

Lastpage

149

Abstract

A boron channel-stop compensation technique using a selective polysilicon etch prior to field oxidation is proposed for CMOS isolation technologies which use polysilicon buffered LOCOS. The stress relief polysilicon layer is selectively removed over the n-well field regions which results in additional boron segregation into the growing field oxide while the polysilicon layer is being oxidized over the p-well field regions. The resulting field threshold voltages are increased by as much as 11.6 and 6.4 V for the p-well and n-well MOS capacitors, respectively.<>

Keywords

CMOS integrated circuits; boron; integrated circuit technology; oxidation; sputter etching; surface segregation; CMOS isolation technologies; Si:B-SiO/sub 2/; channel-stop compensation technique; field oxidation; field threshold voltages; n-well MOS capacitors; n-well field regions; p-well MOS capacitors; p-well field regions; polysilicon buffered LOCOS; selective polysilicon etch; selective segregation; stress relief polysilicon layer; Boron; CMOS technology; Etching; Implants; Isolation technology; MOS devices; Oxidation; Resists; Silicon; Threshold voltage;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.31699

Filename

31699