SPIDER: capacitance modelling for VLSI interconnections

Author

Ning, Zhen-Qiu ; Dewilde, Patrick M.

Author_Institution

Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands

Volume

7

Issue

12

fYear

1988

Firstpage

1221

Lastpage

1228

Abstract

An efficient method is presented to model the parasitic capacitance of VLSI interconnections. It is valid for conductors in a stratified medium which is considered to be a good approximation for the Si-SiO/sub 2/ system of which ICs are made. The model approximates the charge density on the conductors as a continuous function on a web of edges. Each base function in the approximation has the form of a ´spider´ of edges. The model has very low complexity as compared to previously presented models and achieves a high degree of precision within the range of validity of the stratified medium.<>

Keywords

VLSI; capacitance; monolithic integrated circuits; semiconductor device models; silicon; silicon compounds; SPIDER; Si-SiO/sub 2/ system; VLSI interconnections; capacitance modelling; charge density; parasitic capacitance; precision; stratified medium; web; Assembly; Conductors; Electrostatics; Feature extraction; Geometry; Integral equations; Parasitic capacitance; Piecewise linear techniques; Shape; Very large scale integration;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.16800

Filename

16800