Anomalous C-V characteristics of implanted poly MOS structure in n/sup +//p/sup +/ dual-gate CMOS technology

Author

Lu, Chih-Yuan ; Sung, J.M. ; Kirsch, Howard C. ; Hillenius, Steven J. ; Smith, T.E. ; Manchanda, Lalita

Author_Institution

AT&T Bell Labs., Allentown, PA, USA

Volume

10

Issue

5

fYear

1989

fDate

5/1/1989 12:00:00 AM

Firstpage

192

Lastpage

194

Abstract

The C-V characteristics of arsenic-doped polysilicon show a gate-bias dependence of the inversion capacitance and a reduction in the expected value of the inversion capacitance. The characteristics have been investigated with quasistatic and high-frequency C-V as well as conductance measurements of various capacitors that have been subjected to annealing times and temperatures ranging from 900 degrees C/30 min to rapid thermal annealing at 1050 degrees C. The results can be explained by assuming that there is a depletion region forming in the polysilicon due to insufficient activation of the dopant at the polysilicon/oxide surface. The impact of this condition on the device characteristics is shown to be a 20-30% reduction in the G/sub m/ of NMOS transistors with 125-AA Gate oxide thickness.

Keywords

CMOS integrated circuits; annealing; capacitance; integrated circuit technology; inversion layers; NMOS transistors; Si:As; annealing times; anomalous C-V characteristics; conductance measurements; depletion region; gate-bias dependence; implanted poly MOS structure; inversion capacitance; n/sup +//p/sup +/ dual-gate CMOS technology; polysilicon; polysilicon/oxide surface; rapid thermal annealing; Annealing; CMOS process; CMOS technology; Capacitance; Capacitance-voltage characteristics; MOS capacitors; MOSFETs; Schottky diodes; Silicides; Tellurium;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.31717

Filename

31717