An ON-resistance closed form for VDMOS devices

Author

Fernández, J. ; Hidalgo, S. ; Paredes, J. ; Berta, F. ; Rebollo, J. ; Millán, J. ; Serra-Mestres, Francisco

Author_Institution

Centro Nacional de Microelectron., Univ. Autonoma de Barcelona, Spain

Volume

10

Issue

5

fYear

1989

fDate

5/1/1989 12:00:00 AM

Firstpage

212

Lastpage

215

Abstract

An analytical ON-resistance expression for different designs of VDMOS (vertically diffused metal-oxide-semiconductor) devices which takes into consideration the two-dimensional (2-D) nature of the current flow is obtained. This expression differs from other models that overestimate this resistance for large cell spacings. This formulation is in close agreement with experimental points obtained from the interdigitated fabricated structures and with 2-D simulations. Moreover, the effect of a two-level oxide thickness on the ON resistance has been investigated for the interdigitated case.<>

Keywords

insulated gate field effect transistors; metal-insulator-semiconductor devices; power transistors; semiconductor device models; 2D current flow; 2D simulation; ON-resistance closed form; VDMOS devices; interdigitated fabricated structures; models; power transistors; two-level oxide thickness; Conductivity; Contact resistance; Current distribution; Differential equations; Electrodes; Geometry; Immune system; Surface resistance;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.31724

Filename

31724