Image compression if technologies for low power FPDs

We discussed the importance of not only display point of view but also total image systematic point of view approach to reduce power consumption for FPDs. As one of the systematic approaches, we have developed low power interface(IF) techniques using image compression methods, Vertically Differential Encoding (VDE[1], [2]) to reduce the probability of transient bit. The prototype FPGA with the VDE reduced the power consumption of LCD circuit by around 14-15% compared with the conventional methods in the case of 14-in LCD with SXGA resolution.