Interface trap-enhanced gate-induced leakage current in MOSFET

Author

Chen, Ih-Chin ; Teng, C.W. ; Coleman, D.J. ; Nishimura, A.

Author_Institution

Texas Instrum. Inc., Dallas, TX, USA

Volume

10

Issue

5

fYear

1989

fDate

5/1/1989 12:00:00 AM

Firstpage

216

Lastpage

218

Abstract

Interface traps are shown to significantly affect the gate-induced drain-leakage current in a MOSFET or gated diode. The leakage current in a p/sup +/-gated diode can increase by two orders of magnitude when the interface trap density is increased from 10/sup 11/ to 10/sup 12/ cm/sup -2/-eV/sup -1/. The fact that thermal annealing at 300 degrees C can eliminate both the generated interface traps and the excessive leakage current supports the close correlation between the two. The p/sup +/-gated diode is found to be more susceptible to this interface-trap related leakage current than the n/sup +/-device, which can be explained qualitatively by an interface-trap-assisted tunneling model.<>

Keywords

insulated gate field effect transistors; interface electron states; leakage currents; semiconductor device testing; tunnelling; MOSFET; gate-induced leakage current; interface trap density; interface-trap-assisted tunneling; n/sup +/-device; p/sup +/-gated diode; thermal annealing; Annealing; Diodes; Electron traps; Instruments; Leakage current; MOS devices; MOSFET circuits; Silicon; Thin film transistors; Tunneling;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.31725

Filename

31725