Survey of Test Vector Compression Techniques

Author

Touba, Nur A.

Author_Institution

Texas Univ., Austin, TX

Volume

23

Issue

4

fYear

2006

fDate

4/1/2006 12:00:00 AM

Firstpage

294

Lastpage

303

Abstract

Test data compression consists of test vector compression on the input side and response, compaction on the output side. This vector compression has been an active area of research. This article summarizes and categories these techniques. The focus is on hardware-based test vector compression techniques for scan architectures. Test vector compression schemes fall broadly into three categories: code-based schemes use data compression codes to encode test cubes; linear-decompression-based schemes decompress the data using only linear operations (that is LFSRs and XOR networks) and broadcast-scan-based schemes rely on broadcasting the same values to multiple scan chains

Keywords

built-in self test; data compression; integrated circuit design; integrated circuit testing; system-on-chip; broadcast-scan-based scheme; code-based scheme; data compression code; hardware-based test vector compression technique; linear-decompression-based scheme; scan architecture; Automatic test pattern generation; Broadcasting; Built-in self-test; Circuit faults; Circuit testing; Compaction; Data compression; Life testing; Test data compression; Vectors; Test Vector Compression;

fLanguage

English

Journal_Title

Design & Test of Computers, IEEE

Publisher

ieee

ISSN

0740-7475

Type

jour

DOI

10.1109/MDT.2006.105

Filename

1683715