Title :
Blanket LVD tungsten silicide technology for smart power applications
Author :
Shenai, Krishna ; Piacente, Patricia A. ; Saia, Richard ; Baliga, B.Jayant
Author_Institution :
General Electric Co., Schenectady, NY, USA
fDate :
6/1/1989 12:00:00 AM
Abstract :
A high-frequency power MOSFET structure fabricated using blanket deposited LPCVD (low-pressure chemical vapor deposition) WSi/sub 2/ gate and selectively deposited LPCVD tungsten source contact metallurgy is reported. A high-density power MOSFET technology suitable for smart power applications which simultaneously lowers the gate sheet resistance and source contact resistance is discussed. This technology was used to fabricate 30-V and 50-V power FETs with excellent high-frequency performances. The measured specific on-resistance R/sub sp/, specific input capacitance C/sub sp/, and switching times are among the lowest reported in the literature for any power FET structure in this reverse blocking voltage range.<>
Keywords :
MOS integrated circuits; chemical vapour deposition; insulated gate field effect transistors; integrated circuit technology; metallisation; power integrated circuits; power transistors; semiconductor technology; tungsten compounds; 30 to 50 V; W-Si contact; WSi/sub 2/ gate; WSi/sub 2/-Si-SiO/sub 2/-Si gate; blanket deposited LPCVD; gate sheet resistance; high-density power MOSFET technology; high-frequency performances; high-frequency power MOSFET structure; low-pressure chemical vapor deposition; metallisation; policide; power FETs; reverse blocking voltage range; selectively deposited LPCVD; silicide technology; smart power applications; source contact resistance; specific input capacitance; specific on-resistance; switching times; Capacitance measurement; Chemical technology; Chemical vapor deposition; Contact resistance; Electrical resistance measurement; FETs; MOSFET circuits; Power MOSFET; Silicides; Tungsten;
Journal_Title :
Electron Device Letters, IEEE
