Title :
A self-aligned retrograde twin-well structure with buried p/sup +/-layer
Author :
Odanaka, S. ; Yabu, T. ; Shimizu, N. ; Umimoto, H. ; Ohzone, T.
Author_Institution :
Matsushita Electr. Ind. Co., Ltd., Osaka, Japan
fDate :
6/1/1989 12:00:00 AM
Abstract :
The retrograde twin wells and buried p/sup +/ layer are fabricated by a single lithographic step using high-energy ion implantation. The retrograde n-well is self-aligned to the retrograde p-well regions. This simple process allows a scalable CMOS structure for the very tight n/sup +/-to-p/sup +/ spacing. It provides latch-up immunity at the 1.5- mu m n/sup +/-to-p/sup +/ spacing and good isolation characteristics without additional n- and p-channel stops.<>
Keywords :
CMOS integrated circuits; integrated circuit technology; ion implantation; photolithography; 1.5 micron; buried p/sup +/-layer; high-energy ion implantation; isolation characteristics; latch-up immunity; retrograde n-well; retrograde p-well regions; scalable CMOS structure; scaling; self-aligned retrograde twin-well structure; single lithographic step; tight n/sup +/-to-p/sup +/ spacing; Boron; CMOS process; CMOS technology; Epitaxial layers; Fabrication; Implants; Ion implantation; Isolation technology; Resists; Substrates;
Journal_Title :
Electron Device Letters, IEEE
