Author :
Kabza, H. ; Ehinger, K. ; Meister, T.F. ; Meul, H.-W. ; Weger, P. ; Kerner, I. ; Miura-Mattausch, M. ; Schreiter, R. ; Hartwig, D. ; Reisch, M. ; Ohnemus, M. ; Köpl, R. ; Weng, J. ; Klose, H. ; Schaber, H. ; Treitinger, L.
Abstract :
A double-poly-Si self-aligning bipolar process employing 1- mu m lithography is developed for very-high-speed circuit applications. Epilayer doping and thickness are optimized for breakdown voltages and good speed-power performance. Shallow base-emitter profiles are obtained by combining low-energy boron implantation and rapid thermal annealing (RTA) for the emitter drive-in. A transit frequency f/sub T/=14 GHz at V/sub BC/=-1 V and a current-mode-logic (CML) gate delay of 43 ps at 30 fJ are achieved. For an emitter size of 1.0*2.0 mu m/sup 2/ a minimum power-delay product of 15 fJ is calculated. Circuit performance capability is demonstrated by a static frequency divider operating up to 15 GHz.<>
Keywords :
VLSI; bipolar integrated circuits; elemental semiconductors; incoherent light annealing; integrated circuit technology; ion implantation; silicon; 1 micron; 14 GHz; 15 GHz; 15 fJ; 30 fJ; 43 ps; Si; Si:B; breakdown voltages; current mode logic gate delay; emitter drive-in; emitter size; epilayer doping; lithography; low energy implantation; low-power high-speed integrated circuits; polysilicon self-aligning bipolar process; power-delay product; rapid thermal annealing; shallow base emitter profiles; speed-power performance; static frequency divider; transit frequency; Boron; Delay; Doping; Energy consumption; Frequency; High speed integrated circuits; Lithography; Rapid thermal annealing; Rapid thermal processing; Silicon;
