A VLSI chip set for a multiprocessor workstation. I. An RISC microprocessor with coprocessor interface and support for symbolic processing

Author

Lee, David D. ; Kong, Shing I. ; Hill, Mark D. ; Taylor, George S. ; Hodges, David A. ; Katz, Randy H. ; Patterson, David A.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

Volume

24

Issue

6

fYear

1989

fDate

12/1/1989 12:00:00 AM

Firstpage

1688

Lastpage

1698

Abstract

A 40-70 MIPS multiprocessor workstation is considered. VLSI implementation of the central processing unit (CPU) chip, based on reduced instruction set computer (RISC) architecture and with support for LISP, is described. The 1.3-cm² CPU chip uses a direct-mapped 512-b on-chip instruction cache and 138 40-b registers organized in eight overlapping windows to achieve 10 MIPS per processor peak performance with a 10-MHz, four-phase clock

Keywords

CMOS integrated circuits; VLSI; computer interfaces; microprocessor chips; multiprocessing systems; pipeline processing; reduced instruction set computing; workstations; 10 MHz; 40 to 70 MIPS; CMOS IC; CPU chip; LISP support; RISC microprocessor; SPUR processor board; VLSI chip set; architecture; central processing unit; coprocessor interface; direct mapped cache; four-phase clock; multiprocessor workstation; on-chip instruction cache; reduced instruction set computer; symbolic processing support; CMOS technology; Central Processing Unit; Clocks; Coprocessors; Helium; Memory management; Microprocessors; Reduced instruction set computing; Very large scale integration; Workstations;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.45007

Filename

45007