Title :
Simulation Study of High-Performance Modified Saddle MOSFET for Sub-50-nm DRAM Cell Transistors
Author :
Park, Ki-Heung ; Han, Kyoung-Rok ; Kim, Young Min ; Lee, Jong-Ho
Author_Institution :
Sch. of Electron. & Electr. Eng., Kyungpook Nat. Univ., Daegu
Abstract :
A novel modified saddle MOSFET to be applied to sub-50-nm DRAM technology with high performance and easy scalability is proposed, and its characteristics at a given recess open width of 40 nm is studied by device simulation. The proposed device has ~ 21% lower gate capacitance and lower Ioff by two orders of magnitude than a conventional saddle device under nearly the same Ion. In addition, the proposed device showed less threshold voltage sensitivity to the corner shape and lower gate delay time (CV/I) by ~ 30% than the conventional recess channel device while keeping nearly the same Ioff
Keywords :
DRAM chips; MOSFET; nanoelectronics; nanotechnology; semiconductor device models; DRAM cell transistors; device simulation; gate-induced drain leakage; lower gate capacitance; modified saddle MOSFET; nanotechnology; recess channel; Capacitance; Delay effects; Doping profiles; Electrodes; MOSFET circuits; Nanoscale devices; Random access memory; Scalability; Shape; Threshold voltage; DRAM; gate-induced drain leakage (GIDL); recess channel (RC); saddle MOSFET; side-gate;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2006.880833
