A submicrometer high-performance bipolar technology

Author

Chen, Tze-Chiang ; Toh, K.Y. ; Cressler, J.D. ; Warnock, James ; Lu, Pong-Fei ; Tang, Denny D. ; Li, G.P. ; Chuang, Ching-Te ; Ning, Tak H.

Author_Institution

IBM T.J. Watson Res. Center, Yorktown Heights, NY, USA

Volume

10

Issue

8

fYear

1989

Firstpage

364

Lastpage

366

Abstract

The description of a submicrometer self-aligned bipolar technology developed to minimize the device topography and to provide shallow profiles for high-performance (ECL) emitter-coupled logic applications is presented. The technology features 0.8- mu m design rules, planar beakless field oxide, polysilicon-filled deep trench isolation, and the use of rapid thermal annealing (RTA). Conventional ECL circuits with 35-ps gate delays, a novel AC-coupled active-pull-down (API) ECL circuit with 21-ps gate delay, and a 1/128 static frequency divider operated at a maximum clocking frequency of 12.5 GHz are demonstrated.<>

Keywords

bipolar integrated circuits; emitter-coupled logic; frequency dividers; incoherent light annealing; integrated circuit technology; 0.8 micron; 12.5 GHz; 21 ps; 35 ps; ECL circuits; design rules; device topography; emitter-coupled logic applications; gate delays; maximum clocking frequency; planar beakless field oxide; polysilicon-filled deep trench isolation; rapid thermal annealing; shallow profiles; static frequency divider; submicrometer high-performance bipolar technology; Capacitance; Circuits; Clocks; Delay; Electric breakdown; Electric resistance; Frequency conversion; Isolation technology; Rapid thermal annealing; Surfaces;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.31758

Filename

31758