Title :
A Distortion Compensating Flash Analog-to-Digital Conversion Technique
Author :
Srinivas, Venkata ; Pavan, Shanthi ; Lachhwani, Ashish ; Sasidhar, Naga
Author_Institution :
Chennai Design Center
Abstract :
We present a flash ADC design technique that compensates for static nonlinearity of the up-front track-and-hold circuit, so that high speed and high linearity can be obtained at the same time. The proposed technique functions in synergy with a new background comparator offset correction scheme. The excess quantization noise generated due to the background autozero process is derived. We demonstrate the efficacy of our techniques with measurement results for a 160 MSPS 6-bit flash converter designed in a 0.35-mum CMOS process. The ADC consumes 50 mW from a 3.3 V power supply and has an 5.3 effective number of bits (ENOB) at Nyquist
Keywords :
analogue-digital conversion; comparators (circuits); distortion; sample and hold circuits; 0.35 micron; 3.3 V; 50 mW; CMOS process; background autozero process; comparator offset correction scheme; distortion compensation; flash ADC design technique; flash analog-to-digital conversion technique; quantization noise; static nonlinearity; up-front track-and-hold circuit; Analog-digital conversion; Background noise; Circuit noise; Clocks; Disk drives; Instruments; Linearity; Noise generators; Quantization; Signal design; Analog-to-digital conversion; CMOS; bubble correction; disk drive read channel; distortion correction; flash; high-speed; offset correction;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2006.880601
