• DocumentCode
    1167077
  • Title

    A 0.18- \\mu\\hbox {m} CMOS GFSK Analog Front End Using a Bessel-Based Quadrature Discriminator With On-Chip Automatic Tuning

  • Author

    Chi, Baoyong ; Yao, JinKe ; Chiang, Patrick ; Wang, Zhihua

  • Author_Institution
    Inst. of Microelectron., Tsinghua Univ., Beijing, China
  • Volume
    56
  • Issue
    11
  • fYear
    2009
  • Firstpage
    2498
  • Lastpage
    2510
  • Abstract
    A fully integrated 2-MHz Gaussian frequency-shift keying (GFSK) analog front end for low-IF receivers is presented. The analog GFSK demodulation uses a Bessel-based quadrature discriminator and a differentiator-based data decision circuit, eliminating the need for analog-digital converters while enabling high sensitivity and large frequency offset tolerance. The analog front end consists of a fifth-order Butterworth low-pass prefilter, a seven-stage limiter, a quadrature discriminator with a fourth-order Bessel phase-shift network, a fourth-order Butterworth low-pass postfilter, and a differentiator-based data decision circuit. The prefilter, Bessel phase shifter, postfilter, and differentiator are built using identical Gm-C cells and tuned across process variations with a single master-slave phase-locked loop. The GFSK analog front end is implemented in a 1.8-V 0.18-mum CMOS process, recovering 1-Mb/s input data from a 2-MHz GFSK signal with maximum frequency deviation of plusmn160-kHz, frequency offset tolerance from - 38% to +47%, and input sensitivity of -53 dBm and consuming 7 mA of current.
  • Keywords
    Bessel functions; Butterworth filters; CMOS analogue integrated circuits; demodulation; differentiating circuits; discriminators; frequency shift keying; limiters; low-pass filters; phase locked loops; phase shifters; Bessel-based quadrature discriminator; CMOS GFSK analog front end; Gaussian frequency-shift keying; demodulation; differentiator-based data decision circuit; fifth-order Butterworth low-pass prefilter; frequency 2 MHz; frequency offset tolerance; low-IF receiver; master-slave phase-locked loop; on-chip automatic tuning; phase-shift network; seven-stage limiter; size 0.18 mum; voltage 1.8 V; Analog integrated circuits; Gaussian frequency-shift keying (GFSK) demodulator; IF receivers; filter;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems I: Regular Papers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1549-8328
  • Type

    jour

  • DOI
    10.1109/TCSI.2009.2015728
  • Filename
    4785488