A VLSI chip set for a multiprocessor workstation. II. A memory management unit and cache controller

Author

Jeong, Deog-Kyoon ; Wood, David A. ; Gibson, Garth A. ; Eggers, Susan J. ; Hodges, David A. ; Katz, Randy H. ; Patterson, David A.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

Volume

24

Issue

6

fYear

1989

fDate

12/1/1989 12:00:00 AM

Firstpage

1699

Lastpage

1707

Abstract

For pt.I see ibid., vol.24, no.6, p.1688-98 (1989). The authors describe a memory management unit and a cache controller (MMU/CC) for a 40-70-MIPS multiprocessor workstation. The MMU/CC implements a novel memory management scheme, in-cache address translation, which does not require a translation lookaside buffer. It also implements a snooping bus protocol to maintain data consistency across all caches in the system. The chip is implemented in a 1.6-μm double-layer-metal CMOS technology and is being used in a multiprocessor workstation (SPUR) successfully executing a UNIX-like network-based operating system called Sprite as well as many applications, including LISP programs

Keywords

CMOS integrated circuits; VLSI; buffer storage; multiprocessing systems; storage management chips; workstations; 1.6 micron; 40 to 70 MIPS; CMOS technology; LISP programs; SPUR; Sprite; UNIX-like network-based operating system; VLSI chip set; cache controller; double-layer-metal; in-cache address translation; memory management unit; multiprocessor workstation; snooping bus protocol; Access protocols; CMOS process; CMOS technology; Central Processing Unit; Computer aided instruction; Instruments; Memory management; Reduced instruction set computing; Very large scale integration; Workstations;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.45008

Filename

45008