A new frequency synthesis method based on "flying-adder" architecture

The "flying-adder" frequency and phase synthesis architecture was presented in papers published by Mair and Xiu in 2000 and Xiu and You in 2002. This architecture contains many excellent features and it can be implemented/integrated easily in a very large scale integration system. However, it has a drawback of inherent jitter on the output frequency, due to the frequency modulation of the output frequency. This brief presents a new frequency synthesis method that eliminates such jitter. The frequency accuracy of this new architecture is studied; subsequently, the frequency error upper bound is found. Furthermore, it leads to the development of a scheme that can be used to derive the frequency error distribution. The comparison to "integer-N" and "fractional-N" phase-locked loop (PLL) based frequency synthesis techniques is also presented.