DocumentCode :
1167576
Title :
Area-optimized implementation of quadrature direct digital frequency synthesizers on LUT-based FPGAs
Author :
Cardells-Tormo, Francisco ; Valls-Coquillat, Javier
Author_Institution :
Inkjet Commercial Div., Hewlett-Packard, Barcelona, Spain
Volume :
50
Issue :
3
fYear :
2003
fDate :
3/1/2003 12:00:00 AM
Firstpage :
135
Lastpage :
138
Abstract :
This paper deals with an field-programmable gate array (FPGA)-implementation of quadrature direct digital frequency synthesizers (QDDFS), and, in particular, with those based on CORDIC, interpolation, and memory compression. We provide results of maximum throughput, i.e., 302 MHz, when mapping QDDFS architectures on current look-up-table (LUT)-based field-programmable technology. We take into account those VLSI design guidelines that work well on FPGAs and architectural considerations to design efficient (in terms of area and throughput) QDDFS, up to 56% faster than commercial cores. Finally, we present a design map that combines the phase-to-amplitude techniques reviewed in this paper so as to minimize the overall area.
Keywords :
VLSI; digital arithmetic; direct digital synthesis; interpolation; table lookup; 302 MHz; CORDIC; LUT-based FPGAs; QDDFS; VLSI; area-optimized implementation; interpolation; memory compression; phase-to-amplitude techniques; quadrature direct digital frequency synthesizers; throughput; Circuits; Clocks; Digital signal processing; Field programmable gate arrays; Frequency synthesizers; Guidelines; Interpolation; Logic design; Throughput; Very large scale integration;
fLanguage :
English
Journal_Title :
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
Publisher :
ieee
ISSN :
1057-7130
Type :
jour
DOI :
10.1109/TCSII.2003.809716
Filename :
1190051
Link To Document :
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