DocumentCode :
1167638
Title :
Efficient Systolic Implementation of DFT Using a Low-Complexity Convolution-Like Formulation
Author :
Meher, Pramod Kumar
Author_Institution :
Sch. of Comput. Eng., Nanyang Technol. Univ.
Volume :
53
Issue :
8
fYear :
2006
Firstpage :
702
Lastpage :
706
Abstract :
A reduced-complexity algorithm is presented for computation of the discrete Fourier transform, where N-point transform is computed from eight number of nearly (N/8)-point circular-convolution-like operations. A systolic architecture is also derived for very large-scale integration circuit implementation of the proposed algorithm. The proposed architecture is fully pipelined and contains regular and simple locally connected processing elements. It is devoid of complex control structure and is scalable for higher transform lengths. It is observed that the proposed systolic structure involves either less or nearly the same hardware-complexity compared with the corresponding existing systolic structures. In addition, it offers eight times more throughput and significantly low latency compared with the others
Keywords :
VLSI; convolution; digital signal processing chips; discrete Fourier transforms; pipeline processing; systolic arrays; DFT; VLSI; circular-convolution; convolution-like formulation; digital signal processing chip; discrete Fourier transform; reduced-complexity algorithm; systolic array; systolic implementation; systolic structure; very large-scale integration circuit; Application software; Computer architecture; Convolution; Digital signal processing chips; Discrete Fourier transforms; Hardware; Signal design; Signal processing algorithms; Systolic arrays; Very large scale integration; Digital signal processing chip; VLSI; discrete Fourier transform (DFT); systolic array;
fLanguage :
English
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-7747
Type :
jour
DOI :
10.1109/TCSII.2006.875379
Filename :
1683984
Link To Document :
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