Chip layout design of a Josephson LSI circuit for examining high-speed operability by using a standard cell automatic placement and routing technique

Author

Aoyagi, M. ; Hamazaki, Y. ; Nakagawa, H. ; Kurosawa, I. ; Maezawa, M. ; Takada, S.

Author_Institution

Electrotech. Lab., Tsukuba, Japan

Volume

4

Issue

3

fYear

1994

Firstpage

169

Lastpage

176

Abstract

A chip layout design technique for a high-speed Josephson LSI circuit using an automatic placement and routing technique with a standard cell method has been developed. A chip layout design of a Josephson LSI circuit with 1500 gates for examining high-speed operability with a 1 GHz clock frequency has been successfully obtained. Related to high-frequency power on a high-speed Josephson LSI circuit, a dividing method for a circuit and a balancing method for power loads are proposed.<>

Keywords

circuit layout CAD; large scale integration; logic CAD; logic arrays; network routing; superconducting junction devices; superconducting logic circuits; 1 GHz; Josephson LSI circuit; automatic placement; automatic routing; balancing method; chip layout design; clock frequency; dividing method; high-frequency power; high-speed operability; power loads; standard cell; Circuit testing; Clocks; Counting circuits; Frequency; Large scale integration; Power supplies; Read only memory; Standards development; Temperature; Wiring;

fLanguage

English

Journal_Title

Applied Superconductivity, IEEE Transactions on

Publisher

ieee

ISSN

1051-8223

Type

jour

DOI

10.1109/77.317833

Filename

317833