Analog VLSI implementations of auditory wavelet transforms using switched-capacitor circuits

A general scheme for the VLSI implementations of auditory wavelet transforms is proposed using switched-capacitor (SC) circuits. SC circuits are well suited for this application since the dilation constant across different scales of the transform can be precisely implemented and controlled by both the capacitor ratios and the clock frequency. The hardware implementations are made possible by several new circuit designs. Specifically, extremely area-efficient designs are presented to implement very large time-constant filters used to process speech and other acoustic signals. The designs employ a charge differencing technique to reduce significantly the capacitance spread ratios needed in the filter banks. Also, a parasitic-insensitive sum-gain amplifier is designed which samples several inputs at the same phase. The proposed circuits have been fabricated using a 2 μm CMOS n-well process with double polysilicon and double metal. In addition, a 32-channel prototype filter bank (each channel is a 6th order transfer function), covering a frequency range from 0.2 to 6.4 kHz which includes 36 biquads, 32 sum-gain amplifiers and a preemphasis highpass filter, is implemented on a 4.6×6.8 mm² die. The IC measurement results of the proposed circuits and the filter bank show the advantages of such new designs