Negative-resistance MOS transistor

Author

Syrzycki, Marek

Author_Institution

Center for Syst. Sci., Simon Fraser Univ., Burnaby, BC, Canada

Volume

38

Issue

8

fYear

1991

fDate

8/1/1991 12:00:00 AM

Firstpage

1808

Lastpage

1814

Abstract

The author proposes a novel approach for implementing a negative-resistance MOSFET that uses a non-uniform drain-current flow within one integrated structure. This MOS device exhibits a negative output conductance within a specific bias range as a consequence of current sharing between two MOSFETs of different geometries. The author describes a negative-resistance MOS transistor and discusses in detail its principle of operation, design, and electrical characteristics. The MOSFET is a three-terminal voltage-controlled device that consists of two MOS transistors with the same type of channel conductivities and can be implemented either in n-channel or p-channel versions. The proposed device is a compact element that can be fabricated together with other semiconductor devices using a standard CMOS technology

Keywords

CMOS integrated circuits; insulated gate field effect transistors; negative resistance; semiconductor device models; compact element; current sharing between two MOSFETs; design; electrical characteristics; integrated structure; n-MOSFET; negative output conductance; negative-resistance MOS transistor; negative-resistance MOSFET; nonuniform drain current flow; operation; p-MOSFET; same type of channel conductivities; standard CMOS technology; three-terminal voltage-controlled device; CMOS technology; Conductivity; Integrated circuit technology; Inverters; MOS devices; MOSFET circuits; Resistors; Semiconductor devices; Semiconductor diodes; Voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.119019

Filename

119019