DocumentCode :
1169071
Title :
Algorithms for optimizing, two-dimensional symbolic layout compaction
Author :
Wolf, Wayne H. ; Mathews, Robert G. ; Newkirk, John A. ; Dutton, Robert W.
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., CA, USA
Volume :
7
Issue :
4
fYear :
1988
fDate :
4/1/1988 12:00:00 AM
Firstpage :
451
Lastpage :
466
Abstract :
A set of algorithms that implement a technique called Supercompaction is described for two-dimensional compaction layouts. The algorithms minimize a one-dimensional objective function (pitch) by moving objects in the layout in two dimensions. The objective function can be monotonically reduced to a locally minimal value, greatly simplifying search. The algorithms can change the layout by simple motion of components or by automatic jog introduction. Experiments shows that: (1) the number of iterations required to reach a locally optimal layout is very small; (2) the time per iteration is competitive with other compaction techniques; (3) supercompacted layouts are smaller in pitch and area than those produced by existing one-dimensional algorithms; and (4) the results of supercompaction are more predictable than those of existing one-dimensional methods
Keywords :
circuit layout CAD; integrated logic circuits; 2D compaction layouts; Supercompaction; area; automatic jog introduction; compaction techniques; locally minimal value; locally optimal layout; number of iterations; one-dimensional objective function; pitch; predictable; search simplification; simple motion of components; supercompacted layouts; time per iteration; two-dimensional symbolic layout compaction; Algorithm design and analysis; Compaction; Computational efficiency; Helium; Iterative algorithms; Merging; NP-hard problem; Silicon; Testing; Wires;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.3180
Filename :
3180
Link To Document :
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