Design of the Trigger Interface and Distribution Board for TJNAF 12 GeV Upgrade

The design of the Trigger Interface and Distribution (TID) board for the 12 GeV Upgrade at Thomas Jefferson National Accelerator Facility (TJNAF) is described. The TID board distributes a low jitter system clock, synchronized trigger, and synchronized multi-purpose SYNC signal. The TID also initiates readout for the data acquisition front-end crate. With the TID boards, a multi-crate system can be setup for large scale nuclear physics experiments. The TID board can be selectively populated as a Trigger Interface (TI) board, or a Trigger Distribution (TD) board for the 12 GeV upgrade experiments. When the TID is populated as a TI, The TID can be located in the VXS crate and distribute the CLOCK/TRIGGER/SYNC (CTS) through the VXS/P0 connector; it can also be located in the standard VME64 crate, and distribute the CTS through the VME/P2 connector or front panel connectors. It initiates the data acquisition for the front-end crate where the TI is positioned in. When the TID is populated as a TD, it fans out the CTS from the trigger supervisor to the front-end crates through optical fibres. The TD board monitors the trigger processing on the TI boards, and sends feedback to the Trigger Supervisor (TS) board for event readout flow control. A Field Programmable Gate Arrays (FPGA) is utilised on the TID board to provide programmability. The TID board was intensively tested on the bench. The TID production version has been released to industry for contract manufacturing.