Analysis of highly doped collector transistors by using two-dimensional process/device simulation and its application of ECL circuits

A report is presented of the results of an investigation of device parameters and collector-to-emitter breakdown voltages of double polysilicon self-aligned transistors with highly doped collectors using a two-dimensional process/device simulation system. Favourable phosphorous-ion implanting condition for a highly doped pedestal collector was found to achieve a high cutoff frequency as well as low AC base resistance and small base-collector capacitance, thereby keeping the minimum collector-to-emitter breakdown voltage of 3 V. The authors also report ECL circuit performance improvements achieved in experiments that realized a minimum ECL gate delay time of 26.3 ps/gate at switching current of 1.64 mA as a result of process optimization. Moreover, a 1/8 static frequency divider T-F/F has been observed to operate up to a maximum frequency of 15.8 GHz