A new test structure for direct measurement of hot-carrier stress effects on CMOS circuit performance

A test procedure is described that is used for the direct measurement of hot-carrier stress effects on CMOS circuit performance. With this test structure, it is observed that conventional lifetime predictions based on shifts in device DC parameters are too pessimistic compared to the degradation in circuit switching speed. Moreover, the circuit lifetime predictions based on the extrapolations of early shifts in gate delay are subject to potential errors due to a saturation effect, which is believed to result from the dynamic response of generated interface traps