Title :
A new test structure for direct measurement of hot-carrier stress effects on CMOS circuit performance
Author :
Hu, S.C. ; Brassington, M.P.
Author_Institution :
Intel Corp., Santa Clara, CA, USA
fDate :
8/1/1991 12:00:00 AM
Abstract :
A test procedure is described that is used for the direct measurement of hot-carrier stress effects on CMOS circuit performance. With this test structure, it is observed that conventional lifetime predictions based on shifts in device DC parameters are too pessimistic compared to the degradation in circuit switching speed. Moreover, the circuit lifetime predictions based on the extrapolations of early shifts in gate delay are subject to potential errors due to a saturation effect, which is believed to result from the dynamic response of generated interface traps
Keywords :
CMOS integrated circuits; hot carriers; integrated circuit testing; CMOS circuit performance; circuit lifetime predictions; circuit switching speed; dynamic response; hot-carrier stress effects; interface traps; saturation effect; Circuit optimization; Circuit testing; Degradation; Delay effects; Extrapolation; Hot carrier effects; Hot carriers; Life testing; Stress measurement; Switching circuits;
Journal_Title :
Electron Devices, IEEE Transactions on
