A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT

We present an efficient combined single-path delay commutator-feedback (SDC-SDF) radix-2 pipelined fast Fourier transform architecture, which includes log₂ N - 1 SDC stages, and 1 SDF stage. The SDC processing engine is proposed to achieve 100% hardware resource utilization by sharing the common arithmetic resource in the time-multiplexed approach, including both adders and multipliers. Thus, the required number of complex multipliers is reduced to log₄ N - 0.5, compared with log₂ N - 1 for the other radix-2 SDC/SDF architectures. In addition, the proposed architecture requires roughly minimum number of complex adders log₂ N + 1 and complex delay memory 2N + 1.5log₂ N - 1.5.