DocumentCode
1170014
Title
Allocation of multiport memories in data path synthesis
Author
Balakrishnan, M. ; Majumdar, Arun K. ; Banerji, Dilip K. ; Linders, James G. ; Majithia, Jayanti C.
Author_Institution
Dept. of Electr. Comput. Eng., Syracuse Univ., NY, USA
Volume
7
Issue
4
fYear
1988
fDate
4/1/1988 12:00:00 AM
Firstpage
536
Lastpage
540
Abstract
An algorithm to synthesize registers using multiport memories during data-path synthesis is presented. The proposed approach considers not only the access requirements of registers but also their interconnection to operators in order to minimize required interconnections. The same approach can be applied to select the optimum number of buses in a multibus architecture. The method is illustrated with an example
Keywords
storage allocation; access requirements of registers; algorithm to synthesize registers; example; interconnection to operators; memory allocation; minimize required interconnections; multibus architecture; multiport memories in data path synthesis; optimum number of buses; Bridges; Councils; Design automation; Digital systems; Hardware design languages; Information science; Merging; Registers; Silicon compiler; Space exploration;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.3188
Filename
3188
Link To Document