Selectively silicided vertical power DMOSFETs for high-frequency power conversion

Author

Shenai, Krishna ; Piacente, P.A. ; Saia, R. ; Korman, C.S. ; Baliga, B. Jayant

Author_Institution

Corp. Res. & Dev. Center, General Electric Co., Schenectady, NY, USA

Volume

25

Issue

12

fYear

1989

fDate

6/8/1989 12:00:00 AM

Firstpage

784

Lastpage

785

Abstract

A 50 V, 0.56 m Omega cm² vertical power DMOSFET fabricated using selectively silicided gate and source contact regions is reported. The gate-source isolation was provided by anisotropically etched oxide sidewall spacers. This new device structure lowers the source contact resistance considerably by providing a larger contact area and improves the distributed gate RC propagation delay by lowering the gate sheet resistance compared with the conventional heavily doped n⁺-polysilicon gates. Devices with cell density as high as 8 million cells/inch² and die size as large as 200 mil*220 mil and capable of conducting more than 160 A of current have been successfully fabricated with excellent gate yield. These results represent the highest reported forward conductivities for any type of power FET in the 50 V reverse blocking range.

Keywords

insulated gate field effect transistors; power convertors; power transistors; 160 A; 50 V; anisotropically etched oxide sidewall spacers; cell density; die size; distributed gate RC propagation delay; forward conductivities; gate sheet resistance; gate-source isolation; high-frequency power conversion; reverse blocking range; selectively silicided gate; source contact regions; vertical power DMOSFET;

fLanguage

English

Journal_Title

Electronics Letters

Publisher

iet

ISSN

0013-5194

Type

jour

DOI

10.1049/el:19890529

Filename

31897