• DocumentCode
    1170832
  • Title

    Parallel architecture for high-speed Viterbi decoding of convolutional codes

  • Author

    Zhang, Y.F. ; Csillag, P.

  • Author_Institution
    GAPSE/ENDEEIHT, Toulouse, France
  • Volume
    25
  • Issue
    14
  • fYear
    1989
  • fDate
    7/6/1989 12:00:00 AM
  • Firstpage
    887
  • Lastpage
    888
  • Abstract
    A parallelisation algorithm of decoding convolutional codes with the Viterbi algorithm is presented. The architecture of parallel decoding analysed here suits the VLSI realisation very well and allows high-speed decoding.
  • Keywords
    VLSI; decoding; digital integrated circuits; parallel architectures; VLSI realisation; Viterbi algorithm; convolutional codes; decoding convolutional codes; high-speed Viterbi decoding; high-speed decoding; parallel architecture; parallelisation algorithm;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19890595
  • Filename
    31918
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1170832