• DocumentCode
    1170874
  • Title

    Multilevel global placement with congestion control

  • Author

    Chang, Chin-Chih ; Cong, Jason ; Pan, Zhigang ; Yuan, Xin

  • Author_Institution
    Comput. Sci. Dept., Univ. of California, Los Angeles, CA, USA
  • Volume
    22
  • Issue
    4
  • fYear
    2003
  • fDate
    4/1/2003 12:00:00 AM
  • Firstpage
    395
  • Lastpage
    409
  • Abstract
    In this paper, we develop a multilevel global placement algorithm (MGP) integrated with fast incremental global routing for directly updating and optimizing congestion cost during physical hierarchy generation. Fast global routing is achieved using a fast two-bend routing and incremental A-tree algorithm. The routing congestion is modeled by the wire usage estimated by the fast global router. A hierarchical area density control is developed for placing objects with significant size variations. Experimental results show that, compared to GORDIAN-L, the wire length-driven MGP is 4-6.7 times faster and generates slightly better wire length for test circuits larger than 100000 cells. Moreover, the congestion-driven MGP improves wiring overflow by 45%-74% with 5% larger bounding box wire length but 3%-7% shorter routing wire length measured by a graph-based A-tree global router.
  • Keywords
    VLSI; circuit layout CAD; circuit optimisation; integrated circuit interconnections; integrated circuit layout; minimisation; network routing; network topology; VLSI layout; congestion control; congestion cost optimization; deep submicron ICs; fast incremental global routing; fast two-bend routing; hierarchical area density control; incremental A-tree algorithm; multilevel global placement algorithm; physical hierarchy generation; routing congestion modelling; wire usage estimation; Circuit testing; Hardware design languages; Integrated circuit interconnections; Optimization; Process planning; Routing; System performance; Uncertainty; Very large scale integration; Wire;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2003.809661
  • Filename
    1190977