Adiabatic logic based low power multiplexer and demultiplexer

Author

Konwar, Sharmila ; Singha, Thockchom Birjit ; Roy, Sandip ; Vanlalchaka, Reginald H.

Author_Institution

Dept. of Electron. & Commun. Eng., Tezpur Univ., Tezpur, India

fYear

2014

fDate

3-5 Jan. 2014

Firstpage

1

Lastpage

5

Abstract

Minimizing power of digital circuits is always the first priority for VLSI designers. Following this trend, this paper presents a CMOS-based new design approach for a low power adiabatic 8:1 Multiplexer and 1:8 Demultiplexer. Some standard adiabatic logic styles like PFAL, ECRL, 2n2n2p are investigated, which are bettered by the proposed logic. The simulation is carried out in NI-Multisim software at 0.5 μm CMOS technology for frequency range 200MHz - 800MHz.

Keywords

logic circuits; logic design; CMOS-based new design approach; NI-Multisim software; VLSI design; adiabatic logic; complimentary metal oxide semiconductors; digital circuits; frequency 200 MHz to 800 MHz; low power demultiplexer; low power multiplexer; size 0.5 mum; very large scale integrated circuits; CMOS integrated circuits; Computers; Informatics; Multiplexing; Power dissipation; Standards; Transistors; 2n2n2p; Adiabatic logic; Demutilplexer; ECRL; Multiplexer; PFAL; power dissipation; power saving;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Communication and Informatics (ICCCI), 2014 International Conference on

Conference_Location

Coimbatore

Print_ISBN

978-1-4799-2353-3

Type

conf

DOI

10.1109/ICCCI.2014.6921808

Filename

6921808