DocumentCode
1170959
Title
Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost, congestion, and blockages
Author
Hrkic, Milos ; Lillis, John
Author_Institution
Dept. of Comput. Sci., Univ. of Illinois, Chicago, IL, USA
Volume
22
Issue
4
fYear
2003
fDate
4/1/2003 12:00:00 AM
Firstpage
481
Lastpage
491
Abstract
We give an overview of a buffer tree synthesis package which pays particular attention to the following issues: routing and buffer blockages, minimization of interconnect and buffer costs, congestion, exploitation of temporal locality among the sinks, and addressing sink polarity requirements. Experimental results demonstrate the effectiveness of the tool in comparison with previously proposed techniques.
Keywords
buffer circuits; circuit layout CAD; computational complexity; integrated circuit interconnections; integrated circuit layout; network routing; timing; trees (mathematics); Steiner trees; buffer blockages; buffer cost minimization; buffer insertion; buffer tree synthesis package; buffered interconnects synthesis; interconnect cost minimization; routing; timing optimization; Circuit topology; Costs; Councils; Dynamic programming; Engineering profession; Heuristic algorithms; Packaging; Routing; Timing; Wire;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2003.809648
Filename
1190985
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