• DocumentCode
    1171154
  • Title

    Improved a priori interconnect predictions and technology extrapolation in the GTX system

  • Author

    Cao, Yu ; Hu, Chenming ; Huang, Xuejue ; Kahng, Andrew B. ; Markov, Igor L. ; Oliver, Michael ; Stroobandt, Dirk ; Sylvester, Dennis

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, CA, USA
  • Volume
    11
  • Issue
    1
  • fYear
    2003
  • Firstpage
    3
  • Lastpage
    14
  • Abstract
    A priori interconnect prediction and technology extrapolation are closely intertwined. Interconnect predictions are at the core of technology extrapolation models of achievable system power, area density, and speed. Technology extrapolation, in turn, informs a priori interconnect prediction via models of interconnect technology and interconnect optimizations. In this paper, we address the linkage between a priori interconnect prediction and technology extrapolation in two ways. First, we describe how rapid changes in technology, as well as rapid evolution of prediction methods, require a dynamic and flexible framework for technology extrapolation. We then develop a new tool, the GSRC technology extrapolation system (GTX), which allows capture of such knowledge and rapid development of new studies. Second, we identify several "nontraditional" facets of interconnect prediction and quantify their impact on key technology extrapolations. In particular, we explore the effects of interconnect design optimizations such as shield insertion, repeater sizing and repeater staggering, as well as modeling choices for RLC interconnects.
  • Keywords
    VLSI; circuit optimisation; crosstalk; extrapolation; inductance; integrated circuit design; integrated circuit interconnections; integrated circuit modelling; integrated circuit noise; prediction theory; GSRC system; GTX system; RLC interconnect modeling; VLSI; a priori interconnect predictions; crosstalk noise; dynamic flexible framework; inductance; interconnect design optimizations; repeater sizing; repeater staggering; shield insertion; system performance models; technology extrapolation; Couplings; Design methodology; Extrapolation; Integrated circuit interconnections; Power system interconnection; Power system modeling; Predictive models; Repeaters; Very large scale integration; Wire;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2002.808479
  • Filename
    1191307