• DocumentCode
    1171167
  • Title

    Multi-objective optimization of interconnect geometry

  • Author

    Wildman, Raymond A. ; Kramer, Joshua I. ; Weile, Daniel S. ; Christie, Phillip

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Delaware, Newark, DE, USA
  • Volume
    11
  • Issue
    1
  • fYear
    2003
  • Firstpage
    15
  • Lastpage
    23
  • Abstract
    The rapid increase in the number of wiring layers due to improved planarization and metallization techniques permits spatial resources to be traded for improved performance. Yield, power dissipation and propagation delay are all sensitive to the selection of the pitch and width of wires in each layer. As in many other engineering design problems, however, there exists no unique solution which simultaneously optimizes all aspects of system performance. The best that can be achieved is the identification of the optimal surface within the multi-objective performance space. A single design can be chosen from this list a posteriori using additional selection criteria which may depend, for example, on the specific details of the product application. This paper investigates the use of Pareto genetic algorithms to explore the extent of multi-objective optimal surfaces. The tradeoffs between yield, power-dissipation and cycle time for a benchmark netlist are examined as a function of in-plane geometry for a seven-layer interconnect.
  • Keywords
    Pareto distribution; VLSI; circuit optimisation; genetic algorithms; integrated circuit interconnections; integrated circuit layout; IC yield; Pareto genetic algorithms; VLSI design; VLSI interconnect; benchmark netlist; cycle time; in-plane geometry; interconnect geometry; multi-objective optimization; multi-objective performance space; optimal surface; power dissipation; propagation delay; selection criteria; seven-layer interconnect; wiring layers; Design engineering; Design optimization; Geometry; Metallization; Planarization; Power dissipation; Power engineering and energy; Propagation delay; Wires; Wiring;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2002.808460
  • Filename
    1191309