• DocumentCode
    1171182
  • Title

    A comparison of various terminal-gate relationships for interconnect prediction in VLSI circuits

  • Author

    Dambre, Joni ; Verplaetse, Peter ; Stroobandt, Dirk ; Van Campenhout, Jan

  • Author_Institution
    ELIS Dept., Ghent Univ., Belgium
  • Volume
    11
  • Issue
    1
  • fYear
    2003
  • Firstpage
    24
  • Lastpage
    34
  • Abstract
    Over the years, different interpretations of Rent´s rule and different ways of estimating the Rent parameters have emerged. In general, these parameters are extracted from the average terminal-gate relationship for a set of circuit modules. We show that this relationship (the Rent characteristic) strongly depends on the definition of the circuit modules. These can be generated in many different ways, either from the topology of the circuit graph or, in a geometric way, by cutting regions from a circuit layout. The resulting Rent parameters can be quite far apart. This paper discusses the fundamental differences between the topological and the two geometric interpretations of the Rent characteristic that are expected to be most appropriate for current wirelength estimation techniques. Our discussion is based on experimental data, as well as on a theoretical model that can be used to estimate certain geometric Rent characteristics from the topological Rent parameters. Using this model, we derive a theoretical lower limit to the value of the average geometric Rent exponent. We also study the impact of the placement approach and placement quality on the geometric Rent characteristics.
  • Keywords
    VLSI; integrated circuit interconnections; integrated circuit layout; network topology; probability; Rent´s rule; VLSI circuits; VLSI layout; current wirelength estimation techniques; geometric Rent characteristics; geometric interpretations; interconnect complexity; interconnect prediction; module generation; partitioning; placement; terminal-gate relationships; theoretical model; topological Rent parameters; topological interpretations; Analytical models; Circuit topology; Integrated circuit interconnections; Parameter estimation; Solid modeling; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2002.808454
  • Filename
    1191311