DocumentCode :
1171206
Title :
Prelayout interconnect yield prediction
Author :
Christie, Phillip ; De Gyvez, José Pineda
Author_Institution :
Electr. & Comput. Eng. Dept., Univ. of Delaware, Newark, DE, USA
Volume :
11
Issue :
1
fYear :
2003
Firstpage :
55
Lastpage :
59
Abstract :
Functional yield is a term used to describe the percentage of dies on a wafer that are not affected by catastrophic defects. Within the interconnect these defects are usually caused by particle contamination and are divided into bridging defects, which join adjacent wires and cuts, which result in broken wires. Functional yield is therefore determined by the geometry of the routing channels, how these channels are filled with wire and the distribution of defect sizes. Since the wire spacing and width are usually fixed and the distribution of defects within a mature production facility is well known, the problem reduces to estimating individual wire lengths for cuts and to estimating the overlapping distance that two wires share in neighboring sections of the routing grid for bridges. Previous work in this area has analyzed the problem by assuming that all wiring tracks are occupied with wire, leading to overestimates for the probability of failure due to both cuts and bridges. This paper utilizes statistical models of the placement/routing process to provide a more realistic approach for cut and bridge yield estimation. A comparison of the predicted probability of failure within each wiring layer with postlayout data indicate an average error of 20% for cuts and 26% for bridges.
Keywords :
VLSI; integrated circuit interconnections; integrated circuit layout; integrated circuit reliability; integrated circuit yield; network routing; probability; sensitivity analysis; statistical analysis; Rent´s rule; VLSI layout; bridging defects; catastrophic defects; cuts; defect sensitivity analysis; failure probability; functional yield; particle contamination; placement process; prelayout interconnect yield prediction; routing channel geometry; routing grid; shared wire length analysis; statistical models; wire spacing; wire width; yield estimation; Bridges; Contamination; Failure analysis; Geometry; Probability; Production facilities; Routing; Wire; Wiring; Yield estimation;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2002.808461
Filename :
1191317
Link To Document :
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