Title :
Energy-efficient skewed static logic with dual Vt: design and synthesis
Author :
Kim, Chulwoo ; Kim, Ki-Wook ; Kang, Sung-Mo
Author_Institution :
Univ. of Illinois, Urbana-Champaign, IL, USA
Abstract :
In this paper, we describe skewed static logic (S/sup 2/L) with topology-dependent dual Vt which exhibits an energy-efficient operation. S/sup 2/L consumes less dynamic and static power compared to monotonic static (MS) CMOS. Speed degradation of S/sup 2/L, if any, can be offset by an accelerator circuit. We have designed NAND-NOR gate chains using 0.18-/spl mu/m CMOS technology and verified that S/sup 2/L reduces energy-delay product over MS CMOS by 27%-50%. We have also designed 32-b carry-lookahead adders and verified that S/sup 2/L with dual Vt reduces delay by 43% and energy-delay product by 31% for 1-V power supply over conventional CMOS circuit. Synthesis algorithm for S/sup 2/L is developed and the experimental results show S/sup 2/L consumes 23% less power than MS CMOS with minor increase in delay.
Keywords :
CMOS logic circuits; VLSI; adders; circuit CAD; high level synthesis; high-speed integrated circuits; integrated circuit design; low-power electronics; 0.18 micron; 32 bit; NAND-NOR gate chains; accelerator circuit; carry-lookahead adders; dual threshold voltage; energy-efficient operation; leakage-power dissipation; logic synthesis algorithm; low power logic; monotonic static CMOS technology; skewed static logic; topology-dependent dual Vt; Adders; CMOS logic circuits; CMOS technology; Circuit synthesis; Clocks; Energy efficiency; Integrated circuit technology; Logic design; Logic gates; Semiconductor device noise;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2002.800528
